With the advent of the wireless systems, RF power detectors are being used in many RF / millimeter wave integrated circuits. They are critical components in RF transmitters for transmit power control and also have a key role on the RF receivers to measure received signal strength to adjust the amplifier gain. In these blocks, usually RF power amplifier or low noise amplifier’s output power signal is an input to the power detector. The input power of the RF power detector circuit is converted to an analog dc output voltage via logarithmic transfer function in order to achieve a linear-in-dB input-output characteristic and the dc output voltage value indicates the power level of the input signal. In this work, a logarithmic power detection circuit is designed for V/UHF frequency band (30-512 MHz). The architecture of power detector is composed of cascaded limiting amplifiers, half-wave rectifiers, voltage summing circuits and output filtering stages, respectively. To achieve extended dynamic range, outputs of four separate detector stages are summed. The power detector is designed and simulated in UMC 65 nm CMOS technology and consumes 46.7mA from 1.2V supply. The low power circuit is designed using piecewise linear approximation method and has a dynamic range wider than 50 dB. The designed circuit meets the requirements to be used on all the entire V/UHF frequency band radio transceiver applications for aerospace.
Anahtar Kelimeler: Cmos, Power Detector, Successive Detection Logarithmic Amplifier, Limiting Amplifier, Rectifier
|
